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nand_base.c

/*
 *  drivers/mtd/nand.c
 *
 *  Overview:
 *   This is the generic MTD driver for NAND flash devices. It should be
 *   capable of working with almost all NAND chips currently available.
 *   Basic support for AG-AND chips is provided.
 *
 *    Additional technical information is available on
 *    http://www.linux-mtd.infradead.org/tech/nand.html
 *
 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
 *            2002-2006 Thomas Gleixner (tglx@linutronix.de)
 *
 *  Credits:
 *    David Woodhouse for adding multichip support
 *
 *    Aleph One Ltd. and Toby Churchill Ltd. for supporting the
 *    rework for 2K page size chips
 *
 *  TODO:
 *    Enable cached programming for 2k page size chips
 *    Check, if mtd->ecctype should be set to MTD_ECC_HW
 *    if we have HW ecc support.
 *    The AG-AND chips have nice features for speed improvement,
 *    which are not supported yet. Read / program 4 pages in one go.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/compatmac.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/leds.h>
#include <asm/io.h>

#ifdef CONFIG_MTD_PARTITIONS
#include <linux/mtd/partitions.h>
#endif

/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
      .eccbytes = 3,
      .eccpos = {0, 1, 2},
      .oobfree = {
            {.offset = 3,
             .length = 2},
            {.offset = 6,
             .length = 2}}
};

static struct nand_ecclayout nand_oob_16 = {
      .eccbytes = 6,
      .eccpos = {0, 1, 2, 3, 6, 7},
      .oobfree = {
            {.offset = 8,
             . length = 8}}
};

static struct nand_ecclayout nand_oob_64 = {
      .eccbytes = 24,
      .eccpos = {
               40, 41, 42, 43, 44, 45, 46, 47,
               48, 49, 50, 51, 52, 53, 54, 55,
               56, 57, 58, 59, 60, 61, 62, 63},
      .oobfree = {
            {.offset = 2,
             .length = 38}}
};

static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
                     int new_state);

static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
                       struct mtd_oob_ops *ops);

/*
 * For devices which display every fart in the system on a seperate LED. Is
 * compiled away when LED support is disabled.
 */
DEFINE_LED_TRIGGER(nand_led_trigger);

/**
 * nand_release_device - [GENERIC] release chip
 * @mtd:    MTD device structure
 *
 * Deselect, release chip lock and wake up anyone waiting on the device
 */
static void nand_release_device(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;

      /* De-select the NAND device */
      chip->select_chip(mtd, -1);

      /* Release the controller and the chip */
      spin_lock(&chip->controller->lock);
      chip->controller->active = NULL;
      chip->state = FL_READY;
      wake_up(&chip->controller->wq);
      spin_unlock(&chip->controller->lock);
}

/**
 * nand_read_byte - [DEFAULT] read one byte from the chip
 * @mtd:    MTD device structure
 *
 * Default read function for 8bit buswith
 */
static uint8_t nand_read_byte(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;
      return readb(chip->IO_ADDR_R);
}

/**
 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 * @mtd:    MTD device structure
 *
 * Default read function for 16bit buswith with
 * endianess conversion
 */
static uint8_t nand_read_byte16(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;
      return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
}

/**
 * nand_read_word - [DEFAULT] read one word from the chip
 * @mtd:    MTD device structure
 *
 * Default read function for 16bit buswith without
 * endianess conversion
 */
static u16 nand_read_word(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;
      return readw(chip->IO_ADDR_R);
}

/**
 * nand_select_chip - [DEFAULT] control CE line
 * @mtd:    MTD device structure
 * @chipnr: chipnumber to select, -1 for deselect
 *
 * Default select function for 1 chip devices.
 */
static void nand_select_chip(struct mtd_info *mtd, int chipnr)
{
      struct nand_chip *chip = mtd->priv;

      switch (chipnr) {
      case -1:
            chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
            break;
      case 0:
            break;

      default:
            BUG();
      }
}

/**
 * nand_write_buf - [DEFAULT] write buffer to chip
 * @mtd:    MTD device structure
 * @buf:    data buffer
 * @len:    number of bytes to write
 *
 * Default write function for 8bit buswith
 */
static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;

      for (i = 0; i < len; i++)
            writeb(buf[i], chip->IO_ADDR_W);
}

/**
 * nand_read_buf - [DEFAULT] read chip data into buffer
 * @mtd:    MTD device structure
 * @buf:    buffer to store date
 * @len:    number of bytes to read
 *
 * Default read function for 8bit buswith
 */
static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;

      for (i = 0; i < len; i++)
            buf[i] = readb(chip->IO_ADDR_R);
}

/**
 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 * @mtd:    MTD device structure
 * @buf:    buffer containing the data to compare
 * @len:    number of bytes to compare
 *
 * Default verify function for 8bit buswith
 */
static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;

      for (i = 0; i < len; i++)
            if (buf[i] != readb(chip->IO_ADDR_R))
                  return -EFAULT;
      return 0;
}

/**
 * nand_write_buf16 - [DEFAULT] write buffer to chip
 * @mtd:    MTD device structure
 * @buf:    data buffer
 * @len:    number of bytes to write
 *
 * Default write function for 16bit buswith
 */
static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;
      u16 *p = (u16 *) buf;
      len >>= 1;

      for (i = 0; i < len; i++)
            writew(p[i], chip->IO_ADDR_W);

}

/**
 * nand_read_buf16 - [DEFAULT] read chip data into buffer
 * @mtd:    MTD device structure
 * @buf:    buffer to store date
 * @len:    number of bytes to read
 *
 * Default read function for 16bit buswith
 */
static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;
      u16 *p = (u16 *) buf;
      len >>= 1;

      for (i = 0; i < len; i++)
            p[i] = readw(chip->IO_ADDR_R);
}

/**
 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 * @mtd:    MTD device structure
 * @buf:    buffer containing the data to compare
 * @len:    number of bytes to compare
 *
 * Default verify function for 16bit buswith
 */
static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
      int i;
      struct nand_chip *chip = mtd->priv;
      u16 *p = (u16 *) buf;
      len >>= 1;

      for (i = 0; i < len; i++)
            if (p[i] != readw(chip->IO_ADDR_R))
                  return -EFAULT;

      return 0;
}

/**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 * @mtd:    MTD device structure
 * @ofs:    offset from device start
 * @getchip:      0, if the chip is already selected
 *
 * Check, if the block is bad.
 */
static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
{
      int page, chipnr, res = 0;
      struct nand_chip *chip = mtd->priv;
      u16 bad;

      if (getchip) {
            page = (int)(ofs >> chip->page_shift);
            chipnr = (int)(ofs >> chip->chip_shift);

            nand_get_device(chip, mtd, FL_READING);

            /* Select the NAND device */
            chip->select_chip(mtd, chipnr);
      } else
            page = (int)ofs;

      if (chip->options & NAND_BUSWIDTH_16) {
            chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
                        page & chip->pagemask);
            bad = cpu_to_le16(chip->read_word(mtd));
            if (chip->badblockpos & 0x1)
                  bad >>= 8;
            if ((bad & 0xFF) != 0xff)
                  res = 1;
      } else {
            chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
                        page & chip->pagemask);
            if (chip->read_byte(mtd) != 0xff)
                  res = 1;
      }

      if (getchip)
            nand_release_device(mtd);

      return res;
}

/**
 * nand_default_block_markbad - [DEFAULT] mark a block bad
 * @mtd:    MTD device structure
 * @ofs:    offset from device start
 *
 * This is the default implementation, which can be overridden by
 * a hardware specific driver.
*/
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
      struct nand_chip *chip = mtd->priv;
      uint8_t buf[2] = { 0, 0 };
      int block, ret;

      /* Get block number */
      block = ((int)ofs) >> chip->bbt_erase_shift;
      if (chip->bbt)
            chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);

      /* Do we have a flash based bad block table ? */
      if (chip->options & NAND_USE_FLASH_BBT)
            ret = nand_update_bbt(mtd, ofs);
      else {
            /* We write two bytes, so we dont have to mess with 16 bit
             * access
             */
            ofs += mtd->oobsize;
            chip->ops.len = 2;
            chip->ops.datbuf = NULL;
            chip->ops.oobbuf = buf;
            chip->ops.ooboffs = chip->badblockpos & ~0x01;

            ret = nand_do_write_oob(mtd, ofs, &chip->ops);
      }
      if (!ret)
            mtd->ecc_stats.badblocks++;
      return ret;
}

/**
 * nand_check_wp - [GENERIC] check if the chip is write protected
 * @mtd:    MTD device structure
 * Check, if the device is write protected
 *
 * The function expects, that the device is already selected
 */
static int nand_check_wp(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;
      /* Check the WP bit */
      chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
      return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
}

/**
 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 * @mtd:    MTD device structure
 * @ofs:    offset from device start
 * @getchip:      0, if the chip is already selected
 * @allowbbt:     1, if its allowed to access the bbt area
 *
 * Check, if the block is bad. Either by reading the bad block table or
 * calling of the scan function.
 */
static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
                         int allowbbt)
{
      struct nand_chip *chip = mtd->priv;

      if (!chip->bbt)
            return chip->block_bad(mtd, ofs, getchip);

      /* Return info from the table */
      return nand_isbad_bbt(mtd, ofs, allowbbt);
}

/*
 * Wait for the ready pin, after a command
 * The timeout is catched later.
 */
static void nand_wait_ready(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;
      unsigned long timeo = jiffies + 2;

      led_trigger_event(nand_led_trigger, LED_FULL);
      /* wait until command is processed or timeout occures */
      do {
            if (chip->dev_ready(mtd))
                  break;
            touch_softlockup_watchdog();
      } while (time_before(jiffies, timeo));
      led_trigger_event(nand_led_trigger, LED_OFF);
}

/**
 * nand_command - [DEFAULT] Send command to NAND device
 * @mtd:    MTD device structure
 * @command:      the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr:    the page address for this command, -1 if none
 *
 * Send command to NAND device. This function is used for small page
 * devices (256/512 Bytes per page)
 */
static void nand_command(struct mtd_info *mtd, unsigned int command,
                   int column, int page_addr)
{
      register struct nand_chip *chip = mtd->priv;
      int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;

      /*
       * Write out the command to the device.
       */
      if (command == NAND_CMD_SEQIN) {
            int readcmd;

            if (column >= mtd->writesize) {
                  /* OOB area */
                  column -= mtd->writesize;
                  readcmd = NAND_CMD_READOOB;
            } else if (column < 256) {
                  /* First 256 bytes --> READ0 */
                  readcmd = NAND_CMD_READ0;
            } else {
                  column -= 256;
                  readcmd = NAND_CMD_READ1;
            }
            chip->cmd_ctrl(mtd, readcmd, ctrl);
            ctrl &= ~NAND_CTRL_CHANGE;
      }
      chip->cmd_ctrl(mtd, command, ctrl);

      /*
       * Address cycle, when necessary
       */
      ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
      /* Serially input address */
      if (column != -1) {
            /* Adjust columns for 16 bit buswidth */
            if (chip->options & NAND_BUSWIDTH_16)
                  column >>= 1;
            chip->cmd_ctrl(mtd, column, ctrl);
            ctrl &= ~NAND_CTRL_CHANGE;
      }
      if (page_addr != -1) {
            chip->cmd_ctrl(mtd, page_addr, ctrl);
            ctrl &= ~NAND_CTRL_CHANGE;
            chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
            /* One more address cycle for devices > 32MiB */
            if (chip->chipsize > (32 << 20))
                  chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
      }
      chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

      /*
       * program and erase have their own busy handlers
       * status and sequential in needs no delay
       */
      switch (command) {

      case NAND_CMD_PAGEPROG:
      case NAND_CMD_ERASE1:
      case NAND_CMD_ERASE2:
      case NAND_CMD_SEQIN:
      case NAND_CMD_STATUS:
            return;

      case NAND_CMD_RESET:
            if (chip->dev_ready)
                  break;
            udelay(chip->chip_delay);
            chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                         NAND_CTRL_CLE | NAND_CTRL_CHANGE);
            chip->cmd_ctrl(mtd,
                         NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
            while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
            return;

            /* This applies to read commands */
      default:
            /*
             * If we don't have access to the busy pin, we apply the given
             * command delay
             */
            if (!chip->dev_ready) {
                  udelay(chip->chip_delay);
                  return;
            }
      }
      /* Apply this short delay always to ensure that we do wait tWB in
       * any case on any machine. */
      ndelay(100);

      nand_wait_ready(mtd);
}

/**
 * nand_command_lp - [DEFAULT] Send command to NAND large page device
 * @mtd:    MTD device structure
 * @command:      the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr:    the page address for this command, -1 if none
 *
 * Send command to NAND device. This is the version for the new large page
 * devices We dont have the separate regions as we have in the small page
 * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 */
static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
                      int column, int page_addr)
{
      register struct nand_chip *chip = mtd->priv;

      /* Emulate NAND_CMD_READOOB */
      if (command == NAND_CMD_READOOB) {
            column += mtd->writesize;
            command = NAND_CMD_READ0;
      }

      /* Command latch cycle */
      chip->cmd_ctrl(mtd, command & 0xff,
                   NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);

      if (column != -1 || page_addr != -1) {
            int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;

            /* Serially input address */
            if (column != -1) {
                  /* Adjust columns for 16 bit buswidth */
                  if (chip->options & NAND_BUSWIDTH_16)
                        column >>= 1;
                  chip->cmd_ctrl(mtd, column, ctrl);
                  ctrl &= ~NAND_CTRL_CHANGE;
                  chip->cmd_ctrl(mtd, column >> 8, ctrl);
            }
            if (page_addr != -1) {
                  chip->cmd_ctrl(mtd, page_addr, ctrl);
                  chip->cmd_ctrl(mtd, page_addr >> 8,
                               NAND_NCE | NAND_ALE);
                  /* One more address cycle for devices > 128MiB */
                  if (chip->chipsize > (128 << 20))
                        chip->cmd_ctrl(mtd, page_addr >> 16,
                                     NAND_NCE | NAND_ALE);
            }
      }
      chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

      /*
       * program and erase have their own busy handlers
       * status, sequential in, and deplete1 need no delay
       */
      switch (command) {

      case NAND_CMD_CACHEDPROG:
      case NAND_CMD_PAGEPROG:
      case NAND_CMD_ERASE1:
      case NAND_CMD_ERASE2:
      case NAND_CMD_SEQIN:
      case NAND_CMD_RNDIN:
      case NAND_CMD_STATUS:
      case NAND_CMD_DEPLETE1:
            return;

            /*
             * read error status commands require only a short delay
             */
      case NAND_CMD_STATUS_ERROR:
      case NAND_CMD_STATUS_ERROR0:
      case NAND_CMD_STATUS_ERROR1:
      case NAND_CMD_STATUS_ERROR2:
      case NAND_CMD_STATUS_ERROR3:
            udelay(chip->chip_delay);
            return;

      case NAND_CMD_RESET:
            if (chip->dev_ready)
                  break;
            udelay(chip->chip_delay);
            chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                         NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
            chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                         NAND_NCE | NAND_CTRL_CHANGE);
            while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
            return;

      case NAND_CMD_RNDOUT:
            /* No ready / busy check necessary */
            chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
                         NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
            chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                         NAND_NCE | NAND_CTRL_CHANGE);
            return;

      case NAND_CMD_READ0:
            chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
                         NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
            chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                         NAND_NCE | NAND_CTRL_CHANGE);

            /* This applies to read commands */
      default:
            /*
             * If we don't have access to the busy pin, we apply the given
             * command delay
             */
            if (!chip->dev_ready) {
                  udelay(chip->chip_delay);
                  return;
            }
      }

      /* Apply this short delay always to ensure that we do wait tWB in
       * any case on any machine. */
      ndelay(100);

      nand_wait_ready(mtd);
}

/**
 * nand_get_device - [GENERIC] Get chip for selected access
 * @chip:   the nand chip descriptor
 * @mtd:    MTD device structure
 * @new_state:    the state which is requested
 *
 * Get the device and lock it for exclusive access
 */
static int
nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
{
      spinlock_t *lock = &chip->controller->lock;
      wait_queue_head_t *wq = &chip->controller->wq;
      DECLARE_WAITQUEUE(wait, current);
 retry:
      spin_lock(lock);

      /* Hardware controller shared among independend devices */
      /* Hardware controller shared among independend devices */
      if (!chip->controller->active)
            chip->controller->active = chip;

      if (chip->controller->active == chip && chip->state == FL_READY) {
            chip->state = new_state;
            spin_unlock(lock);
            return 0;
      }
      if (new_state == FL_PM_SUSPENDED) {
            spin_unlock(lock);
            return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
      }
      set_current_state(TASK_UNINTERRUPTIBLE);
      add_wait_queue(wq, &wait);
      spin_unlock(lock);
      schedule();
      remove_wait_queue(wq, &wait);
      goto retry;
}

/**
 * nand_wait - [DEFAULT]  wait until the command is done
 * @mtd:    MTD device structure
 * @chip:   NAND chip structure
 *
 * Wait for command done. This applies to erase and program only
 * Erase can take up to 400ms and program up to 20ms according to
 * general NAND and SmartMedia specs
 */
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{

      unsigned long timeo = jiffies;
      int status, state = chip->state;

      if (state == FL_ERASING)
            timeo += (HZ * 400) / 1000;
      else
            timeo += (HZ * 20) / 1000;

      led_trigger_event(nand_led_trigger, LED_FULL);

      /* Apply this short delay always to ensure that we do wait tWB in
       * any case on any machine. */
      ndelay(100);

      if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
            chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
      else
            chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);

      while (time_before(jiffies, timeo)) {
            if (chip->dev_ready) {
                  if (chip->dev_ready(mtd))
                        break;
            } else {
                  if (chip->read_byte(mtd) & NAND_STATUS_READY)
                        break;
            }
            cond_resched();
      }
      led_trigger_event(nand_led_trigger, LED_OFF);

      status = (int)chip->read_byte(mtd);
      return status;
}

/**
 * nand_read_page_raw - [Intern] read raw page data without ecc
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    buffer to store read data
 */
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                        uint8_t *buf)
{
      chip->read_buf(mtd, buf, mtd->writesize);
      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
      return 0;
}

/**
 * nand_read_page_swecc - {REPLACABLE] software ecc based page read function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    buffer to store read data
 */
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                        uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      uint8_t *p = buf;
      uint8_t *ecc_calc = chip->buffers.ecccalc;
      uint8_t *ecc_code = chip->buffers.ecccode;
      int *eccpos = chip->ecc.layout->eccpos;

      nand_read_page_raw(mtd, chip, buf);

      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
            chip->ecc.calculate(mtd, p, &ecc_calc[i]);

      for (i = 0; i < chip->ecc.total; i++)
            ecc_code[i] = chip->oob_poi[eccpos[i]];

      eccsteps = chip->ecc.steps;
      p = buf;

      for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
            int stat;

            stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
            if (stat == -1)
                  mtd->ecc_stats.failed++;
            else
                  mtd->ecc_stats.corrected += stat;
      }
      return 0;
}

/**
 * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    buffer to store read data
 *
 * Not for syndrome calculating ecc controllers which need a special oob layout
 */
static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                        uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      uint8_t *p = buf;
      uint8_t *ecc_calc = chip->buffers.ecccalc;
      uint8_t *ecc_code = chip->buffers.ecccode;
      int *eccpos = chip->ecc.layout->eccpos;

      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
            chip->ecc.hwctl(mtd, NAND_ECC_READ);
            chip->read_buf(mtd, p, eccsize);
            chip->ecc.calculate(mtd, p, &ecc_calc[i]);
      }
      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

      for (i = 0; i < chip->ecc.total; i++)
            ecc_code[i] = chip->oob_poi[eccpos[i]];

      eccsteps = chip->ecc.steps;
      p = buf;

      for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
            int stat;

            stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
            if (stat == -1)
                  mtd->ecc_stats.failed++;
            else
                  mtd->ecc_stats.corrected += stat;
      }
      return 0;
}

/**
 * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    buffer to store read data
 *
 * The hw generator calculates the error syndrome automatically. Therefor
 * we need a special oob layout and handling.
 */
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                           uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      uint8_t *p = buf;
      uint8_t *oob = chip->oob_poi;

      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
            int stat;

            chip->ecc.hwctl(mtd, NAND_ECC_READ);
            chip->read_buf(mtd, p, eccsize);

            if (chip->ecc.prepad) {
                  chip->read_buf(mtd, oob, chip->ecc.prepad);
                  oob += chip->ecc.prepad;
            }

            chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
            chip->read_buf(mtd, oob, eccbytes);
            stat = chip->ecc.correct(mtd, p, oob, NULL);

            if (stat == -1)
                  mtd->ecc_stats.failed++;
            else
                  mtd->ecc_stats.corrected += stat;

            oob += eccbytes;

            if (chip->ecc.postpad) {
                  chip->read_buf(mtd, oob, chip->ecc.postpad);
                  oob += chip->ecc.postpad;
            }
      }

      /* Calculate remaining oob bytes */
      i = mtd->oobsize - (oob - chip->oob_poi);
      if (i)
            chip->read_buf(mtd, oob, i);

      return 0;
}

/**
 * nand_transfer_oob - [Internal] Transfer oob to client buffer
 * @chip:   nand chip structure
 * @oob:    oob destination address
 * @ops:    oob ops structure
 */
static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
                          struct mtd_oob_ops *ops)
{
      size_t len = ops->ooblen;

      switch(ops->mode) {

      case MTD_OOB_PLACE:
      case MTD_OOB_RAW:
            memcpy(oob, chip->oob_poi + ops->ooboffs, len);
            return oob + len;

      case MTD_OOB_AUTO: {
            struct nand_oobfree *free = chip->ecc.layout->oobfree;
            uint32_t boffs = 0, roffs = ops->ooboffs;
            size_t bytes = 0;

            for(; free->length && len; free++, len -= bytes) {
                  /* Read request not from offset 0 ? */
                  if (unlikely(roffs)) {
                        if (roffs >= free->length) {
                              roffs -= free->length;
                              continue;
                        }
                        boffs = free->offset + roffs;
                        bytes = min_t(size_t, len,
                                    (free->length - roffs));
                        roffs = 0;
                  } else {
                        bytes = min_t(size_t, len, free->length);
                        boffs = free->offset;
                  }
                  memcpy(oob, chip->oob_poi + boffs, bytes);
                  oob += bytes;
            }
            return oob;
      }
      default:
            BUG();
      }
      return NULL;
}

/**
 * nand_do_read_ops - [Internal] Read data with ECC
 *
 * @mtd:    MTD device structure
 * @from:   offset to read from
 * @ops:    oob ops structure
 *
 * Internal function. Called with chip held.
 */
static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
                      struct mtd_oob_ops *ops)
{
      int chipnr, page, realpage, col, bytes, aligned;
      struct nand_chip *chip = mtd->priv;
      struct mtd_ecc_stats stats;
      int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
      int sndcmd = 1;
      int ret = 0;
      uint32_t readlen = ops->len;
      uint8_t *bufpoi, *oob, *buf;

      stats = mtd->ecc_stats;

      chipnr = (int)(from >> chip->chip_shift);
      chip->select_chip(mtd, chipnr);

      realpage = (int)(from >> chip->page_shift);
      page = realpage & chip->pagemask;

      col = (int)(from & (mtd->writesize - 1));
      chip->oob_poi = chip->buffers.oobrbuf;

      buf = ops->datbuf;
      oob = ops->oobbuf;

      while(1) {
            bytes = min(mtd->writesize - col, readlen);
            aligned = (bytes == mtd->writesize);

            /* Is the current page in the buffer ? */
            if (realpage != chip->pagebuf || oob) {
                  bufpoi = aligned ? buf : chip->buffers.databuf;

                  if (likely(sndcmd)) {
                        chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
                        sndcmd = 0;
                  }

                  /* Now read the page into the buffer */
                  ret = chip->ecc.read_page(mtd, chip, bufpoi);
                  if (ret < 0)
                        break;

                  /* Transfer not aligned data */
                  if (!aligned) {
                        chip->pagebuf = realpage;
                        memcpy(buf, chip->buffers.databuf + col, bytes);
                  }

                  buf += bytes;

                  if (unlikely(oob)) {
                        /* Raw mode does data:oob:data:oob */
                        if (ops->mode != MTD_OOB_RAW)
                              oob = nand_transfer_oob(chip, oob, ops);
                        else
                              buf = nand_transfer_oob(chip, buf, ops);
                  }

                  if (!(chip->options & NAND_NO_READRDY)) {
                        /*
                         * Apply delay or wait for ready/busy pin. Do
                         * this before the AUTOINCR check, so no
                         * problems arise if a chip which does auto
                         * increment is marked as NOAUTOINCR by the
                         * board driver.
                         */
                        if (!chip->dev_ready)
                              udelay(chip->chip_delay);
                        else
                              nand_wait_ready(mtd);
                  }
            } else {
                  memcpy(buf, chip->buffers.databuf + col, bytes);
                  buf += bytes;
            }

            readlen -= bytes;

            if (!readlen)
                  break;

            /* For subsequent reads align to page boundary. */
            col = 0;
            /* Increment page address */
            realpage++;

            page = realpage & chip->pagemask;
            /* Check, if we cross a chip boundary */
            if (!page) {
                  chipnr++;
                  chip->select_chip(mtd, -1);
                  chip->select_chip(mtd, chipnr);
            }

            /* Check, if the chip supports auto page increment
             * or if we have hit a block boundary.
             */
            if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
                  sndcmd = 1;
      }

      ops->retlen = ops->len - (size_t) readlen;

      if (ret)
            return ret;

      if (mtd->ecc_stats.failed - stats.failed)
            return -EBADMSG;

      return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
}

/**
 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
 * @mtd:    MTD device structure
 * @from:   offset to read from
 * @len:    number of bytes to read
 * @retlen: pointer to variable to store the number of read bytes
 * @buf:    the databuffer to put data
 *
 * Get hold of the chip and call nand_do_read
 */
static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
                 size_t *retlen, uint8_t *buf)
{
      struct nand_chip *chip = mtd->priv;
      int ret;

      /* Do not allow reads past end of device */
      if ((from + len) > mtd->size)
            return -EINVAL;
      if (!len)
            return 0;

      nand_get_device(chip, mtd, FL_READING);

      chip->ops.len = len;
      chip->ops.datbuf = buf;
      chip->ops.oobbuf = NULL;

      ret = nand_do_read_ops(mtd, from, &chip->ops);

      *retlen = chip->ops.retlen;

      nand_release_device(mtd);

      return ret;
}

/**
 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @page:   page number to read
 * @sndcmd: flag whether to issue read command or not
 */
static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
                       int page, int sndcmd)
{
      if (sndcmd) {
            chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
            sndcmd = 0;
      }
      chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
      return sndcmd;
}

/**
 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
 *                    with syndromes
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @page:   page number to read
 * @sndcmd: flag whether to issue read command or not
 */
static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                          int page, int sndcmd)
{
      uint8_t *buf = chip->oob_poi;
      int length = mtd->oobsize;
      int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
      int eccsize = chip->ecc.size;
      uint8_t *bufpoi = buf;
      int i, toread, sndrnd = 0, pos;

      chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
      for (i = 0; i < chip->ecc.steps; i++) {
            if (sndrnd) {
                  pos = eccsize + i * (eccsize + chunk);
                  if (mtd->writesize > 512)
                        chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
                  else
                        chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
            } else
                  sndrnd = 1;
            toread = min_t(int, length, chunk);
            chip->read_buf(mtd, bufpoi, toread);
            bufpoi += toread;
            length -= toread;
      }
      if (length > 0)
            chip->read_buf(mtd, bufpoi, length);

      return 1;
}

/**
 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @page:   page number to write
 */
static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
                        int page)
{
      int status = 0;
      const uint8_t *buf = chip->oob_poi;
      int length = mtd->oobsize;

      chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
      chip->write_buf(mtd, buf, length);
      /* Send command to program the OOB data */
      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

      status = chip->waitfunc(mtd, chip);

      return status & NAND_STATUS_FAIL ? -EIO : 0;
}

/**
 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
 *                     with syndrome - only for large page flash !
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @page:   page number to write
 */
static int nand_write_oob_syndrome(struct mtd_info *mtd,
                           struct nand_chip *chip, int page)
{
      int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
      int eccsize = chip->ecc.size, length = mtd->oobsize;
      int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
      const uint8_t *bufpoi = chip->oob_poi;

      /*
       * data-ecc-data-ecc ... ecc-oob
       * or
       * data-pad-ecc-pad-data-pad .... ecc-pad-oob
       */
      if (!chip->ecc.prepad && !chip->ecc.postpad) {
            pos = steps * (eccsize + chunk);
            steps = 0;
      } else
            pos = eccsize;

      chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
      for (i = 0; i < steps; i++) {
            if (sndcmd) {
                  if (mtd->writesize <= 512) {
                        uint32_t fill = 0xFFFFFFFF;

                        len = eccsize;
                        while (len > 0) {
                              int num = min_t(int, len, 4);
                              chip->write_buf(mtd, (uint8_t *)&fill,
                                          num);
                              len -= num;
                        }
                  } else {
                        pos = eccsize + i * (eccsize + chunk);
                        chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
                  }
            } else
                  sndcmd = 1;
            len = min_t(int, length, chunk);
            chip->write_buf(mtd, bufpoi, len);
            bufpoi += len;
            length -= len;
      }
      if (length > 0)
            chip->write_buf(mtd, bufpoi, length);

      chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
      status = chip->waitfunc(mtd, chip);

      return status & NAND_STATUS_FAIL ? -EIO : 0;
}

/**
 * nand_do_read_oob - [Intern] NAND read out-of-band
 * @mtd:    MTD device structure
 * @from:   offset to read from
 * @ops:    oob operations description structure
 *
 * NAND read out-of-band data from the spare area
 */
static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
                      struct mtd_oob_ops *ops)
{
      int page, realpage, chipnr, sndcmd = 1;
      struct nand_chip *chip = mtd->priv;
      int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
      int readlen = ops->len;
      uint8_t *buf = ops->oobbuf;

      DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
            (unsigned long long)from, readlen);

      chipnr = (int)(from >> chip->chip_shift);
      chip->select_chip(mtd, chipnr);

      /* Shift to get page */
      realpage = (int)(from >> chip->page_shift);
      page = realpage & chip->pagemask;

      chip->oob_poi = chip->buffers.oobrbuf;

      while(1) {
            sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
            buf = nand_transfer_oob(chip, buf, ops);

            if (!(chip->options & NAND_NO_READRDY)) {
                  /*
                   * Apply delay or wait for ready/busy pin. Do this
                   * before the AUTOINCR check, so no problems arise if a
                   * chip which does auto increment is marked as
                   * NOAUTOINCR by the board driver.
                   */
                  if (!chip->dev_ready)
                        udelay(chip->chip_delay);
                  else
                        nand_wait_ready(mtd);
            }

            readlen -= ops->ooblen;
            if (!readlen)
                  break;

            /* Increment page address */
            realpage++;

            page = realpage & chip->pagemask;
            /* Check, if we cross a chip boundary */
            if (!page) {
                  chipnr++;
                  chip->select_chip(mtd, -1);
                  chip->select_chip(mtd, chipnr);
            }

            /* Check, if the chip supports auto page increment
             * or if we have hit a block boundary.
             */
            if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
                  sndcmd = 1;
      }

      ops->retlen = ops->len;
      return 0;
}

/**
 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
 * @mtd:    MTD device structure
 * @from:   offset to read from
 * @ops:    oob operation description structure
 *
 * NAND read data and/or out-of-band data
 */
static int nand_read_oob(struct mtd_info *mtd, loff_t from,
                   struct mtd_oob_ops *ops)
{
      int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
                   uint8_t *buf) = NULL;
      struct nand_chip *chip = mtd->priv;
      int ret = -ENOTSUPP;

      ops->retlen = 0;

      /* Do not allow reads past end of device */
      if ((from + ops->len) > mtd->size) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
                  "Attempt read beyond end of device\n");
            return -EINVAL;
      }

      nand_get_device(chip, mtd, FL_READING);

      switch(ops->mode) {
      case MTD_OOB_PLACE:
      case MTD_OOB_AUTO:
            break;

      case MTD_OOB_RAW:
            /* Replace the read_page algorithm temporary */
            read_page = chip->ecc.read_page;
            chip->ecc.read_page = nand_read_page_raw;
            break;

      default:
            goto out;
      }

      if (!ops->datbuf)
            ret = nand_do_read_oob(mtd, from, ops);
      else
            ret = nand_do_read_ops(mtd, from, ops);

      if (unlikely(ops->mode == MTD_OOB_RAW))
            chip->ecc.read_page = read_page;
 out:
      nand_release_device(mtd);
      return ret;
}


/**
 * nand_write_page_raw - [Intern] raw page write function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    data buffer
 */
static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                        const uint8_t *buf)
{
      chip->write_buf(mtd, buf, mtd->writesize);
      chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
}

/**
 * nand_write_page_swecc - {REPLACABLE] software ecc based page write function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    data buffer
 */
static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                          const uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      uint8_t *ecc_calc = chip->buffers.ecccalc;
      const uint8_t *p = buf;
      int *eccpos = chip->ecc.layout->eccpos;

      /* Software ecc calculation */
      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
            chip->ecc.calculate(mtd, p, &ecc_calc[i]);

      for (i = 0; i < chip->ecc.total; i++)
            chip->oob_poi[eccpos[i]] = ecc_calc[i];

      nand_write_page_raw(mtd, chip, buf);
}

/**
 * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    data buffer
 */
static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                          const uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      uint8_t *ecc_calc = chip->buffers.ecccalc;
      const uint8_t *p = buf;
      int *eccpos = chip->ecc.layout->eccpos;

      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
            chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
            chip->write_buf(mtd, p, eccsize);
            chip->ecc.calculate(mtd, p, &ecc_calc[i]);
      }

      for (i = 0; i < chip->ecc.total; i++)
            chip->oob_poi[eccpos[i]] = ecc_calc[i];

      chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
}

/**
 * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write
 * @mtd:    mtd info structure
 * @chip:   nand chip info structure
 * @buf:    data buffer
 *
 * The hw generator calculates the error syndrome automatically. Therefor
 * we need a special oob layout and handling.
 */
static void nand_write_page_syndrome(struct mtd_info *mtd,
                            struct nand_chip *chip, const uint8_t *buf)
{
      int i, eccsize = chip->ecc.size;
      int eccbytes = chip->ecc.bytes;
      int eccsteps = chip->ecc.steps;
      const uint8_t *p = buf;
      uint8_t *oob = chip->oob_poi;

      for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {

            chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
            chip->write_buf(mtd, p, eccsize);

            if (chip->ecc.prepad) {
                  chip->write_buf(mtd, oob, chip->ecc.prepad);
                  oob += chip->ecc.prepad;
            }

            chip->ecc.calculate(mtd, p, oob);
            chip->write_buf(mtd, oob, eccbytes);
            oob += eccbytes;

            if (chip->ecc.postpad) {
                  chip->write_buf(mtd, oob, chip->ecc.postpad);
                  oob += chip->ecc.postpad;
            }
      }

      /* Calculate remaining oob bytes */
      i = mtd->oobsize - (oob - chip->oob_poi);
      if (i)
            chip->write_buf(mtd, oob, i);
}

/**
 * nand_write_page - [INTERNAL] write one page
 * @mtd:    MTD device structure
 * @chip:   NAND chip descriptor
 * @buf:    the data to write
 * @page:   page number to write
 * @cached: cached programming
 */
static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
                     const uint8_t *buf, int page, int cached)
{
      int status;

      chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);

      chip->ecc.write_page(mtd, chip, buf);

      /*
       * Cached progamming disabled for now, Not sure if its worth the
       * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
       */
      cached = 0;

      if (!cached || !(chip->options & NAND_CACHEPRG)) {

            chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
            status = chip->waitfunc(mtd, chip);
            /*
             * See if operation failed and additional status checks are
             * available
             */
            if ((status & NAND_STATUS_FAIL) && (chip->errstat))
                  status = chip->errstat(mtd, chip, FL_WRITING, status,
                                     page);

            if (status & NAND_STATUS_FAIL)
                  return -EIO;
      } else {
            chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
            status = chip->waitfunc(mtd, chip);
      }

#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
      /* Send command to read back the data */
      chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

      if (chip->verify_buf(mtd, buf, mtd->writesize))
            return -EIO;
#endif
      return 0;
}

/**
 * nand_fill_oob - [Internal] Transfer client buffer to oob
 * @chip:   nand chip structure
 * @oob:    oob data buffer
 * @ops:    oob ops structure
 */
static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
                          struct mtd_oob_ops *ops)
{
      size_t len = ops->ooblen;

      switch(ops->mode) {

      case MTD_OOB_PLACE:
      case MTD_OOB_RAW:
            memcpy(chip->oob_poi + ops->ooboffs, oob, len);
            return oob + len;

      case MTD_OOB_AUTO: {
            struct nand_oobfree *free = chip->ecc.layout->oobfree;
            uint32_t boffs = 0, woffs = ops->ooboffs;
            size_t bytes = 0;

            for(; free->length && len; free++, len -= bytes) {
                  /* Write request not from offset 0 ? */
                  if (unlikely(woffs)) {
                        if (woffs >= free->length) {
                              woffs -= free->length;
                              continue;
                        }
                        boffs = free->offset + woffs;
                        bytes = min_t(size_t, len,
                                    (free->length - woffs));
                        woffs = 0;
                  } else {
                        bytes = min_t(size_t, len, free->length);
                        boffs = free->offset;
                  }
                  memcpy(chip->oob_poi + boffs, oob, bytes);
                  oob += bytes;
            }
            return oob;
      }
      default:
            BUG();
      }
      return NULL;
}

#define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0

/**
 * nand_do_write_ops - [Internal] NAND write with ECC
 * @mtd:    MTD device structure
 * @to:           offset to write to
 * @ops:    oob operations description structure
 *
 * NAND write with ECC
 */
static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
                       struct mtd_oob_ops *ops)
{
      int chipnr, realpage, page, blockmask;
      struct nand_chip *chip = mtd->priv;
      uint32_t writelen = ops->len;
      uint8_t *oob = ops->oobbuf;
      uint8_t *buf = ops->datbuf;
      int bytes = mtd->writesize;
      int ret;

      ops->retlen = 0;

      /* reject writes, which are not page aligned */
      if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
            printk(KERN_NOTICE "nand_write: "
                   "Attempt to write not page aligned data\n");
            return -EINVAL;
      }

      if (!writelen)
            return 0;

      chipnr = (int)(to >> chip->chip_shift);
      chip->select_chip(mtd, chipnr);

      /* Check, if it is write protected */
      if (nand_check_wp(mtd))
            return -EIO;

      realpage = (int)(to >> chip->page_shift);
      page = realpage & chip->pagemask;
      blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;

      /* Invalidate the page cache, when we write to the cached page */
      if (to <= (chip->pagebuf << chip->page_shift) &&
          (chip->pagebuf << chip->page_shift) < (to + ops->len))
            chip->pagebuf = -1;

      chip->oob_poi = chip->buffers.oobwbuf;

      while(1) {
            int cached = writelen > bytes && page != blockmask;

            if (unlikely(oob))
                  oob = nand_fill_oob(chip, oob, ops);

            ret = nand_write_page(mtd, chip, buf, page, cached);
            if (ret)
                  break;

            writelen -= bytes;
            if (!writelen)
                  break;

            buf += bytes;
            realpage++;

            page = realpage & chip->pagemask;
            /* Check, if we cross a chip boundary */
            if (!page) {
                  chipnr++;
                  chip->select_chip(mtd, -1);
                  chip->select_chip(mtd, chipnr);
            }
      }

      if (unlikely(oob))
            memset(chip->oob_poi, 0xff, mtd->oobsize);

      ops->retlen = ops->len - writelen;
      return ret;
}

/**
 * nand_write - [MTD Interface] NAND write with ECC
 * @mtd:    MTD device structure
 * @to:           offset to write to
 * @len:    number of bytes to write
 * @retlen: pointer to variable to store the number of written bytes
 * @buf:    the data to write
 *
 * NAND write with ECC
 */
static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
                    size_t *retlen, const uint8_t *buf)
{
      struct nand_chip *chip = mtd->priv;
      int ret;

      /* Do not allow reads past end of device */
      if ((to + len) > mtd->size)
            return -EINVAL;
      if (!len)
            return 0;

      nand_get_device(chip, mtd, FL_WRITING);

      chip->ops.len = len;
      chip->ops.datbuf = (uint8_t *)buf;
      chip->ops.oobbuf = NULL;

      ret = nand_do_write_ops(mtd, to, &chip->ops);

      *retlen = chip->ops.retlen;

      nand_release_device(mtd);

      return ret;
}

/**
 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
 * @mtd:    MTD device structure
 * @to:           offset to write to
 * @ops:    oob operation description structure
 *
 * NAND write out-of-band
 */
static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
                       struct mtd_oob_ops *ops)
{
      int chipnr, page, status;
      struct nand_chip *chip = mtd->priv;

      DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
            (unsigned int)to, (int)ops->len);

      /* Do not allow write past end of page */
      if ((ops->ooboffs + ops->len) > mtd->oobsize) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
                  "Attempt to write past end of page\n");
            return -EINVAL;
      }

      chipnr = (int)(to >> chip->chip_shift);
      chip->select_chip(mtd, chipnr);

      /* Shift to get page */
      page = (int)(to >> chip->page_shift);

      /*
       * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
       * of my DiskOnChip 2000 test units) will clear the whole data page too
       * if we don't do this. I have no clue why, but I seem to have 'fixed'
       * it in the doc2000 driver in August 1999.  dwmw2.
       */
      chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);

      /* Check, if it is write protected */
      if (nand_check_wp(mtd))
            return -EROFS;

      /* Invalidate the page cache, if we write to the cached page */
      if (page == chip->pagebuf)
            chip->pagebuf = -1;

      chip->oob_poi = chip->buffers.oobwbuf;
      memset(chip->oob_poi, 0xff, mtd->oobsize);
      nand_fill_oob(chip, ops->oobbuf, ops);
      status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
      memset(chip->oob_poi, 0xff, mtd->oobsize);

      if (status)
            return status;

      ops->retlen = ops->len;

      return 0;
}

/**
 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
 * @mtd:    MTD device structure
 * @to:           offset to write to
 * @ops:    oob operation description structure
 */
static int nand_write_oob(struct mtd_info *mtd, loff_t to,
                    struct mtd_oob_ops *ops)
{
      void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
                    const uint8_t *buf) = NULL;
      struct nand_chip *chip = mtd->priv;
      int ret = -ENOTSUPP;

      ops->retlen = 0;

      /* Do not allow writes past end of device */
      if ((to + ops->len) > mtd->size) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
                  "Attempt read beyond end of device\n");
            return -EINVAL;
      }

      nand_get_device(chip, mtd, FL_WRITING);

      switch(ops->mode) {
      case MTD_OOB_PLACE:
      case MTD_OOB_AUTO:
            break;

      case MTD_OOB_RAW:
            /* Replace the write_page algorithm temporary */
            write_page = chip->ecc.write_page;
            chip->ecc.write_page = nand_write_page_raw;
            break;

      default:
            goto out;
      }

      if (!ops->datbuf)
            ret = nand_do_write_oob(mtd, to, ops);
      else
            ret = nand_do_write_ops(mtd, to, ops);

      if (unlikely(ops->mode == MTD_OOB_RAW))
            chip->ecc.write_page = write_page;
 out:
      nand_release_device(mtd);
      return ret;
}

/**
 * single_erease_cmd - [GENERIC] NAND standard block erase command function
 * @mtd:    MTD device structure
 * @page:   the page address of the block which will be erased
 *
 * Standard erase command for NAND chips
 */
static void single_erase_cmd(struct mtd_info *mtd, int page)
{
      struct nand_chip *chip = mtd->priv;
      /* Send commands to erase a block */
      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
      chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
}

/**
 * multi_erease_cmd - [GENERIC] AND specific block erase command function
 * @mtd:    MTD device structure
 * @page:   the page address of the block which will be erased
 *
 * AND multi block erase command function
 * Erase 4 consecutive blocks
 */
static void multi_erase_cmd(struct mtd_info *mtd, int page)
{
      struct nand_chip *chip = mtd->priv;
      /* Send commands to erase a block */
      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
      chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
      chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
}

/**
 * nand_erase - [MTD Interface] erase block(s)
 * @mtd:    MTD device structure
 * @instr:  erase instruction
 *
 * Erase one ore more blocks
 */
static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
{
      return nand_erase_nand(mtd, instr, 0);
}

#define BBT_PAGE_MASK   0xffffff3f
/**
 * nand_erase_nand - [Internal] erase block(s)
 * @mtd:    MTD device structure
 * @instr:  erase instruction
 * @allowbbt:     allow erasing the bbt area
 *
 * Erase one ore more blocks
 */
int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
                int allowbbt)
{
      int page, len, status, pages_per_block, ret, chipnr;
      struct nand_chip *chip = mtd->priv;
      int rewrite_bbt[NAND_MAX_CHIPS]={0};
      unsigned int bbt_masked_page = 0xffffffff;

      DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
            (unsigned int)instr->addr, (unsigned int)instr->len);

      /* Start address must align on block boundary */
      if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
            return -EINVAL;
      }

      /* Length must align on block boundary */
      if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
                  "Length not block aligned\n");
            return -EINVAL;
      }

      /* Do not allow erase past end of device */
      if ((instr->len + instr->addr) > mtd->size) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
                  "Erase past end of device\n");
            return -EINVAL;
      }

      instr->fail_addr = 0xffffffff;

      /* Grab the lock and see if the device is available */
      nand_get_device(chip, mtd, FL_ERASING);

      /* Shift to get first page */
      page = (int)(instr->addr >> chip->page_shift);
      chipnr = (int)(instr->addr >> chip->chip_shift);

      /* Calculate pages in each block */
      pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);

      /* Select the NAND device */
      chip->select_chip(mtd, chipnr);

      /* Check, if it is write protected */
      if (nand_check_wp(mtd)) {
            DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
                  "Device is write protected!!!\n");
            instr->state = MTD_ERASE_FAILED;
            goto erase_exit;
      }

      /*
       * If BBT requires refresh, set the BBT page mask to see if the BBT
       * should be rewritten. Otherwise the mask is set to 0xffffffff which
       * can not be matched. This is also done when the bbt is actually
       * erased to avoid recusrsive updates
       */
      if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
            bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;

      /* Loop through the pages */
      len = instr->len;

      instr->state = MTD_ERASING;

      while (len) {
            /*
             * heck if we have a bad block, we do not erase bad blocks !
             */
            if (nand_block_checkbad(mtd, ((loff_t) page) <<
                              chip->page_shift, 0, allowbbt)) {
                  printk(KERN_WARNING "nand_erase: attempt to erase a "
                         "bad block at page 0x%08x\n", page);
                  instr->state = MTD_ERASE_FAILED;
                  goto erase_exit;
            }

            /*
             * Invalidate the page cache, if we erase the block which
             * contains the current cached page
             */
            if (page <= chip->pagebuf && chip->pagebuf <
                (page + pages_per_block))
                  chip->pagebuf = -1;

            chip->erase_cmd(mtd, page & chip->pagemask);

            status = chip->waitfunc(mtd, chip);

            /*
             * See if operation failed and additional status checks are
             * available
             */
            if ((status & NAND_STATUS_FAIL) && (chip->errstat))
                  status = chip->errstat(mtd, chip, FL_ERASING,
                                     status, page);

            /* See if block erase succeeded */
            if (status & NAND_STATUS_FAIL) {
                  DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
                        "Failed erase, page 0x%08x\n", page);
                  instr->state = MTD_ERASE_FAILED;
                  instr->fail_addr = (page << chip->page_shift);
                  goto erase_exit;
            }

            /*
             * If BBT requires refresh, set the BBT rewrite flag to the
             * page being erased
             */
            if (bbt_masked_page != 0xffffffff &&
                (page & BBT_PAGE_MASK) == bbt_masked_page)
                      rewrite_bbt[chipnr] = (page << chip->page_shift);

            /* Increment page address and decrement length */
            len -= (1 << chip->phys_erase_shift);
            page += pages_per_block;

            /* Check, if we cross a chip boundary */
            if (len && !(page & chip->pagemask)) {
                  chipnr++;
                  chip->select_chip(mtd, -1);
                  chip->select_chip(mtd, chipnr);

                  /*
                   * If BBT requires refresh and BBT-PERCHIP, set the BBT
                   * page mask to see if this BBT should be rewritten
                   */
                  if (bbt_masked_page != 0xffffffff &&
                      (chip->bbt_td->options & NAND_BBT_PERCHIP))
                        bbt_masked_page = chip->bbt_td->pages[chipnr] &
                              BBT_PAGE_MASK;
            }
      }
      instr->state = MTD_ERASE_DONE;

 erase_exit:

      ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
      /* Do call back function */
      if (!ret)
            mtd_erase_callback(instr);

      /* Deselect and wake up anyone waiting on the device */
      nand_release_device(mtd);

      /*
       * If BBT requires refresh and erase was successful, rewrite any
       * selected bad block tables
       */
      if (bbt_masked_page == 0xffffffff || ret)
            return ret;

      for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
            if (!rewrite_bbt[chipnr])
                  continue;
            /* update the BBT for chip */
            DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
                  "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
                  chip->bbt_td->pages[chipnr]);
            nand_update_bbt(mtd, rewrite_bbt[chipnr]);
      }

      /* Return more or less happy */
      return ret;
}

/**
 * nand_sync - [MTD Interface] sync
 * @mtd:    MTD device structure
 *
 * Sync is actually a wait for chip ready function
 */
static void nand_sync(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;

      DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");

      /* Grab the lock and see if the device is available */
      nand_get_device(chip, mtd, FL_SYNCING);
      /* Release it and go back */
      nand_release_device(mtd);
}

/**
 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
 * @mtd:    MTD device structure
 * @offs:   offset relative to mtd start
 */
static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
{
      /* Check for invalid offset */
      if (offs > mtd->size)
            return -EINVAL;

      return nand_block_checkbad(mtd, offs, 1, 0);
}

/**
 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
 * @mtd:    MTD device structure
 * @ofs:    offset relative to mtd start
 */
static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
      struct nand_chip *chip = mtd->priv;
      int ret;

      if ((ret = nand_block_isbad(mtd, ofs))) {
            /* If it was bad already, return success and do nothing. */
            if (ret > 0)
                  return 0;
            return ret;
      }

      return chip->block_markbad(mtd, ofs);
}

/**
 * nand_suspend - [MTD Interface] Suspend the NAND flash
 * @mtd:    MTD device structure
 */
static int nand_suspend(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;

      return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
}

/**
 * nand_resume - [MTD Interface] Resume the NAND flash
 * @mtd:    MTD device structure
 */
static void nand_resume(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;

      if (chip->state == FL_PM_SUSPENDED)
            nand_release_device(mtd);
      else
            printk(KERN_ERR "nand_resume() called for a chip which is not "
                   "in suspended state\n");
}

/*
 * Set default functions
 */
static void nand_set_defaults(struct nand_chip *chip, int busw)
{
      /* check for proper chip_delay setup, set 20us if not */
      if (!chip->chip_delay)
            chip->chip_delay = 20;

      /* check, if a user supplied command function given */
      if (chip->cmdfunc == NULL)
            chip->cmdfunc = nand_command;

      /* check, if a user supplied wait function given */
      if (chip->waitfunc == NULL)
            chip->waitfunc = nand_wait;

      if (!chip->select_chip)
            chip->select_chip = nand_select_chip;
      if (!chip->read_byte)
            chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
      if (!chip->read_word)
            chip->read_word = nand_read_word;
      if (!chip->block_bad)
            chip->block_bad = nand_block_bad;
      if (!chip->block_markbad)
            chip->block_markbad = nand_default_block_markbad;
      if (!chip->write_buf)
            chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
      if (!chip->read_buf)
            chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
      if (!chip->verify_buf)
            chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
      if (!chip->scan_bbt)
            chip->scan_bbt = nand_default_bbt;

      if (!chip->controller) {
            chip->controller = &chip->hwcontrol;
            spin_lock_init(&chip->controller->lock);
            init_waitqueue_head(&chip->controller->wq);
      }

}

/*
 * Get the flash and manufacturer id and lookup if the type is supported
 */
static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
                                      struct nand_chip *chip,
                                      int busw, int *maf_id)
{
      struct nand_flash_dev *type = NULL;
      int i, dev_id, maf_idx;

      /* Select the device */
      chip->select_chip(mtd, 0);

      /* Send the command for reading device ID */
      chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);

      /* Read manufacturer and device IDs */
      *maf_id = chip->read_byte(mtd);
      dev_id = chip->read_byte(mtd);

      /* Lookup the flash id */
      for (i = 0; nand_flash_ids[i].name != NULL; i++) {
            if (dev_id == nand_flash_ids[i].id) {
                  type =  &nand_flash_ids[i];
                  break;
            }
      }

      if (!type)
            return ERR_PTR(-ENODEV);

      if (!mtd->name)
            mtd->name = type->name;

      chip->chipsize = type->chipsize << 20;

      /* Newer devices have all the information in additional id bytes */
      if (!type->pagesize) {
            int extid;
            /* The 3rd id byte contains non relevant data ATM */
            extid = chip->read_byte(mtd);
            /* The 4th id byte is the important one */
            extid = chip->read_byte(mtd);
            /* Calc pagesize */
            mtd->writesize = 1024 << (extid & 0x3);
            extid >>= 2;
            /* Calc oobsize */
            mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
            extid >>= 2;
            /* Calc blocksize. Blocksize is multiples of 64KiB */
            mtd->erasesize = (64 * 1024) << (extid & 0x03);
            extid >>= 2;
            /* Get buswidth information */
            busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;

      } else {
            /*
             * Old devices have chip data hardcoded in the device id table
             */
            mtd->erasesize = type->erasesize;
            mtd->writesize = type->pagesize;
            mtd->oobsize = mtd->writesize / 32;
            busw = type->options & NAND_BUSWIDTH_16;
      }

      /* Try to identify manufacturer */
      for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
            if (nand_manuf_ids[maf_idx].id == *maf_id)
                  break;
      }

      /*
       * Check, if buswidth is correct. Hardware drivers should set
       * chip correct !
       */
      if (busw != (chip->options & NAND_BUSWIDTH_16)) {
            printk(KERN_INFO "NAND device: Manufacturer ID:"
                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
                   dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
            printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
                   (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
                   busw ? 16 : 8);
            return ERR_PTR(-EINVAL);
      }

      /* Calculate the address shift from the page size */
      chip->page_shift = ffs(mtd->writesize) - 1;
      /* Convert chipsize to number of pages per chip -1. */
      chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;

      chip->bbt_erase_shift = chip->phys_erase_shift =
            ffs(mtd->erasesize) - 1;
      chip->chip_shift = ffs(chip->chipsize) - 1;

      /* Set the bad block position */
      chip->badblockpos = mtd->writesize > 512 ?
            NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;

      /* Get chip options, preserve non chip based options */
      chip->options &= ~NAND_CHIPOPTIONS_MSK;
      chip->options |= type->options & NAND_CHIPOPTIONS_MSK;

      /*
       * Set chip as a default. Board drivers can override it, if necessary
       */
      chip->options |= NAND_NO_AUTOINCR;

      /* Check if chip is a not a samsung device. Do not clear the
       * options for chips which are not having an extended id.
       */
      if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
            chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;

      /* Check for AND chips with 4 page planes */
      if (chip->options & NAND_4PAGE_ARRAY)
            chip->erase_cmd = multi_erase_cmd;
      else
            chip->erase_cmd = single_erase_cmd;

      /* Do not replace user supplied command function ! */
      if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
            chip->cmdfunc = nand_command_lp;

      printk(KERN_INFO "NAND device: Manufacturer ID:"
             " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
             nand_manuf_ids[maf_idx].name, type->name);

      return type;
}

/* module_text_address() isn't exported, and it's mostly a pointless
   test if this is a module _anyway_ -- they'd have to try _really_ hard
   to call us from in-kernel code if the core NAND support is modular. */
#ifdef MODULE
#define caller_is_module() (1)
#else
#define caller_is_module() \
      module_text_address((unsigned long)__builtin_return_address(0))
#endif

/**
 * nand_scan - [NAND Interface] Scan for the NAND device
 * @mtd:    MTD device structure
 * @maxchips:     Number of chips to scan for
 *
 * This fills out all the uninitialized function pointers
 * with the defaults.
 * The flash ID is read and the mtd/chip structures are
 * filled with the appropriate values.
 * The mtd->owner field must be set to the module of the caller
 *
 */
int nand_scan(struct mtd_info *mtd, int maxchips)
{
      int i, busw, nand_maf_id;
      struct nand_chip *chip = mtd->priv;
      struct nand_flash_dev *type;

      /* Many callers got this wrong, so check for it for a while... */
      if (!mtd->owner && caller_is_module()) {
            printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
            BUG();
      }

      /* Get buswidth to select the correct functions */
      busw = chip->options & NAND_BUSWIDTH_16;
      /* Set the default functions */
      nand_set_defaults(chip, busw);

      /* Read the flash type */
      type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);

      if (IS_ERR(type)) {
            printk(KERN_WARNING "No NAND device found!!!\n");
            chip->select_chip(mtd, -1);
            return PTR_ERR(type);
      }

      /* Check for a chip array */
      for (i = 1; i < maxchips; i++) {
            chip->select_chip(mtd, i);
            /* Send the command for reading device ID */
            chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
            /* Read manufacturer and device IDs */
            if (nand_maf_id != chip->read_byte(mtd) ||
                type->id != chip->read_byte(mtd))
                  break;
      }
      if (i > 1)
            printk(KERN_INFO "%d NAND chips detected\n", i);

      /* Store the number of chips and calc total size for mtd */
      chip->numchips = i;
      mtd->size = i * chip->chipsize;

      /* Preset the internal oob write buffer */
      memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize);

      /*
       * If no default placement scheme is given, select an appropriate one
       */
      if (!chip->ecc.layout) {
            switch (mtd->oobsize) {
            case 8:
                  chip->ecc.layout = &nand_oob_8;
                  break;
            case 16:
                  chip->ecc.layout = &nand_oob_16;
                  break;
            case 64:
                  chip->ecc.layout = &nand_oob_64;
                  break;
            default:
                  printk(KERN_WARNING "No oob scheme defined for "
                         "oobsize %d\n", mtd->oobsize);
                  BUG();
            }
      }

      /*
       * check ECC mode, default to software if 3byte/512byte hardware ECC is
       * selected and we have 256 byte pagesize fallback to software ECC
       */
      switch (chip->ecc.mode) {
      case NAND_ECC_HW:
            /* Use standard hwecc read page function ? */
            if (!chip->ecc.read_page)
                  chip->ecc.read_page = nand_read_page_hwecc;
            if (!chip->ecc.write_page)
                  chip->ecc.write_page = nand_write_page_hwecc;
            if (!chip->ecc.read_oob)
                  chip->ecc.read_oob = nand_read_oob_std;
            if (!chip->ecc.write_oob)
                  chip->ecc.write_oob = nand_write_oob_std;

      case NAND_ECC_HW_SYNDROME:
            if (!chip->ecc.calculate || !chip->ecc.correct ||
                !chip->ecc.hwctl) {
                  printk(KERN_WARNING "No ECC functions supplied, "
                         "Hardware ECC not possible\n");
                  BUG();
            }
            /* Use standard syndrome read/write page function ? */
            if (!chip->ecc.read_page)
                  chip->ecc.read_page = nand_read_page_syndrome;
            if (!chip->ecc.write_page)
                  chip->ecc.write_page = nand_write_page_syndrome;
            if (!chip->ecc.read_oob)
                  chip->ecc.read_oob = nand_read_oob_syndrome;
            if (!chip->ecc.write_oob)
                  chip->ecc.write_oob = nand_write_oob_syndrome;

            if (mtd->writesize >= chip->ecc.size)
                  break;
            printk(KERN_WARNING "%d byte HW ECC not possible on "
                   "%d byte page size, fallback to SW ECC\n",
                   chip->ecc.size, mtd->writesize);
            chip->ecc.mode = NAND_ECC_SOFT;

      case NAND_ECC_SOFT:
            chip->ecc.calculate = nand_calculate_ecc;
            chip->ecc.correct = nand_correct_data;
            chip->ecc.read_page = nand_read_page_swecc;
            chip->ecc.write_page = nand_write_page_swecc;
            chip->ecc.read_oob = nand_read_oob_std;
            chip->ecc.write_oob = nand_write_oob_std;
            chip->ecc.size = 256;
            chip->ecc.bytes = 3;
            break;

      case NAND_ECC_NONE:
            printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
                   "This is not recommended !!\n");
            chip->ecc.read_page = nand_read_page_raw;
            chip->ecc.write_page = nand_write_page_raw;
            chip->ecc.read_oob = nand_read_oob_std;
            chip->ecc.write_oob = nand_write_oob_std;
            chip->ecc.size = mtd->writesize;
            chip->ecc.bytes = 0;
            break;
      default:
            printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
                   chip->ecc.mode);
            BUG();
      }

      /*
       * The number of bytes available for a client to place data into
       * the out of band area
       */
      chip->ecc.layout->oobavail = 0;
      for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
            chip->ecc.layout->oobavail +=
                  chip->ecc.layout->oobfree[i].length;

      /*
       * Set the number of read / write steps for one page depending on ECC
       * mode
       */
      chip->ecc.steps = mtd->writesize / chip->ecc.size;
      if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
            printk(KERN_WARNING "Invalid ecc parameters\n");
            BUG();
      }
      chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;

      /* Initialize state */
      chip->state = FL_READY;

      /* De-select the device */
      chip->select_chip(mtd, -1);

      /* Invalidate the pagebuffer reference */
      chip->pagebuf = -1;

      /* Fill in remaining MTD driver data */
      mtd->type = MTD_NANDFLASH;
      mtd->flags = MTD_CAP_NANDFLASH;
      mtd->ecctype = MTD_ECC_SW;
      mtd->erase = nand_erase;
      mtd->point = NULL;
      mtd->unpoint = NULL;
      mtd->read = nand_read;
      mtd->write = nand_write;
      mtd->read_oob = nand_read_oob;
      mtd->write_oob = nand_write_oob;
      mtd->sync = nand_sync;
      mtd->lock = NULL;
      mtd->unlock = NULL;
      mtd->suspend = nand_suspend;
      mtd->resume = nand_resume;
      mtd->block_isbad = nand_block_isbad;
      mtd->block_markbad = nand_block_markbad;

      /* propagate ecc.layout to mtd_info */
      mtd->ecclayout = chip->ecc.layout;

      /* Check, if we should skip the bad block table scan */
      if (chip->options & NAND_SKIP_BBTSCAN)
            return 0;

      /* Build bad block table */
      return chip->scan_bbt(mtd);
}

/**
 * nand_release - [NAND Interface] Free resources held by the NAND device
 * @mtd:    MTD device structure
*/
void nand_release(struct mtd_info *mtd)
{
      struct nand_chip *chip = mtd->priv;

#ifdef CONFIG_MTD_PARTITIONS
      /* Deregister partitions */
      del_mtd_partitions(mtd);
#endif
      /* Deregister the device */
      del_mtd_device(mtd);

      /* Free bad block table memory */
      kfree(chip->bbt);
}

EXPORT_SYMBOL_GPL(nand_scan);
EXPORT_SYMBOL_GPL(nand_release);

static int __init nand_base_init(void)
{
      led_trigger_register_simple("nand-disk", &nand_led_trigger);
      return 0;
}

static void __exit nand_base_exit(void)
{
      led_trigger_unregister_simple(nand_led_trigger);
}

module_init(nand_base_init);
module_exit(nand_base_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
MODULE_DESCRIPTION("Generic NAND flash driver code");

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